1. Field of the Invention
The present invention relates to electronic semiconductor devices and methods of fabrication, and, more particularly, to threshold adjustment for insulated gate field effect transistors and integrated circuits with such transistors.
2. Description of the Related Art
Very large scale integrated semiconductor circuits such as dRAMs are typically fabricated with metal oxide silicon field effect transistors (MOSFETs). The electrical characteristics of MOSFETs of a given size can be adjusted by techniques such as use of lightly doped drains, threshold adjustment implants, polysilicon gates, and so forth. As the number of MOSFETs per chip is increased, the MOSFET feature size is downscaled, and this leads to thinner gate oxides, shallower junctions, increased doping levels, lower operating voltages, etc. and makes the achievement of good electrical characteristics more difficult. See generally H. Shichijo, A Re-Examination of Practical Scalability Limits of N-Channel and P-Channel MOS Devices for VLSI. 1981 IEDM 210 and references cited therein.
The threshold adjustment implant has been commonplace since the advent of ion implantation, and the first technique widely used was implanting p or n type dopants through the gate oxide prior to deposition of the gate. This technique has the problem of exposing the gate oxide to several processing steps, and the gate oxide integrity is compromised. This problem is exacerbated by downscaling due to the decreasing thickness of the gate oxide.
An alternative threshold adjustment implant technique is to implant through a dummy gate oxide which is later stripped and the true gate oxide grown followed immediately by the gate deposition. (Note that the range of boron implanted at 30 keV is about 1,000 .ANG., which is too large for threshold adjustment if the implant were into the silicon without a dummy gate oxide, and that 30 keV is the lowest practical implant energy for obtaining high beam currents.) This technique yields good gate oxide integrity, but the growth of the gate oxide subsequent to the threshold implant implies high temperature processing steps and a diffusion of the threshold implant dopants. Further, implanted boron segregates into the oxide during the growth; so the net effect is to have an undesirably deep implant. This leads to an increased body effect in n channel transistors and an increased short channel threshold rolloff due to a deeper buried channel.
A variation of the alternative threshold adjustment implant technique is to grow the gate oxide at low temperature to limit the implant dopant diffusion. However, low temperature gate oxide growth leads to generally degraded quality of both the gate oxide and the interface of the gate oxide with the silicon. In particular, both the oxide fixed charge and the interfacial trapped charge increase with decreasing processing temperature; further, oxide density and intrinsic stress increase substantially for oxides grown below 1,000.degree. C. See G.Lucovsky et al. Low-Temperature Growth of Silicon Dioxide Films: A Study of Chemical Bonding by Ellipsometry and Infrared Spectroscopy, 5 J. Vac. Sci. Tech. B 530 (1987).
Thus it is a problem in the known threshold adjustment implant methods and threshold adjusted devices to have both good quality gate oxide plus a tight, shallow dopant profile.